2016/09/30 (五) 14:20 - 沈中安 教授(台科大 電子工程系) - Algorithms and Architectures of Efficient Receivers for Memory-Dominated MIMO Communication Systems
Topic： Algorithms and Architectures of Efficient Receivers for Memory-Dominated MIMO Communication Systems
Date&Time：2016/09/30 (五) 14:20
Speaker：沈中安 教授(台科大 電子工程系)
Location：清華大學台達館 R216
Abstract：
Multiple-Input Multiple-Output (MIMO) has been recognized as a promising technology to improve the quality of service and/or to achieve high data rate for wireless communication systems. However, the lucrative features of MIMO communications come along with the costs of significantly increased system complexity. This talk presents efficient designs for the spatial multiplexing MIMO receivers at both the algorithm and VLSI architecture levels.
Specifically, this talk introduces an algorithm and VLSI architecture to perform joint detection and decoding for MIMO systems utilizing convolutional and Turbo codes. The simulation and implementation results will be illustrated showing that this scheme can significantly reduce complexity while jointly considering the MIMO detector and channel decoder. Moreover, an error-resilient MIMO detection approach is depicted. This structure is error-resilient in a sense that it can achieve near-optimal performance in the presence of both channel noise and memory errors due to aggressive voltage scaling. This scheme greatly improve the energy efficiency in a memory-dominated MIMO communication system.
Date&Time：2016/09/30 (五) 14:20
Speaker：沈中安 教授(台科大 電子工程系)
Location：清華大學台達館 R216
Abstract：
Multiple-Input Multiple-Output (MIMO) has been recognized as a promising technology to improve the quality of service and/or to achieve high data rate for wireless communication systems. However, the lucrative features of MIMO communications come along with the costs of significantly increased system complexity. This talk presents efficient designs for the spatial multiplexing MIMO receivers at both the algorithm and VLSI architecture levels.
Specifically, this talk introduces an algorithm and VLSI architecture to perform joint detection and decoding for MIMO systems utilizing convolutional and Turbo codes. The simulation and implementation results will be illustrated showing that this scheme can significantly reduce complexity while jointly considering the MIMO detector and channel decoder. Moreover, an error-resilient MIMO detection approach is depicted. This structure is error-resilient in a sense that it can achieve near-optimal performance in the presence of both channel noise and memory errors due to aggressive voltage scaling. This scheme greatly improve the energy efficiency in a memory-dominated MIMO communication system.