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Date&Time : 

2021 / 11 / 5 (Fri) 14:20 - 16:20

Location : 

Online Course

Speaker : 

 徐茂修 博士(Dr. Patrick Hsu)

敦泰電子股份有限公司 新事業開發處(FocalTech) 

Topic : 

High speed IC design system of re-timer applying on 224 Gbps line rate

Abstract : 

Multi-gigahertz serial links, with progressively increasing bitrates, suffer from signal distortion (Inter symbol Interference, or ISI) due to PCB and package copper and dielectric losses. Other distortions also occur due to impedance discontinuities in the channels, such as vias, connectors, and packages. While a Serializer-Deserializer (SerDes) receiver (Rx for short) is designed to compensate for most of these distortions, and create an internal eye open enough for reliable sampling, bit rates are rising faster than Rx, PCB, or package High Density Interconnect (HDI) technologies can keep up with. The result is that total channel reach is decreasing. Using expensive PCB materials to reduce loss will be reaching its dielectric limits soon, and adds significant cost. Next generation buses, such as PCI Express (PCIe) and USB type C to very high speed rate data. For the above reasons, and this presentation describes the mixed-signal (analog/digital) “Re-timers” (both protocol-aware) to achieve this opened eye diagram. The block will include CTLE(continuous time linear equalizer) ,DFE(Decision feedback equalizer), CDR(clock data recovery) IC design methods. A re-timer re-transmits data anew, with new equalization, and new jitter content, unrelated analog-wise to the input bit stream, while intelligent Re-timers are Protocol-aware, and TxEQ Training capable.

Bio :

Mao-Hsiu Hsu received the Ph.D. degree in Department of Electronic and Computer Engineering from National Taiwan University of Science and Technology, Taiwan, in 2005. Dr. Hsu joined FocalTech Electronics in 2019 as a Senior Technical Manager in Hsinchu Science Park, and was the Taiwan Ming Chuan University assistant professor in Department of Information and Telecommunications Engineering in 2006. In 1997, he joined Motorola crystal filter and oscillator design as an engineer and then from 1998 to 2006, he was a staff engineer in Chung-hwa Telecom Co., Ltd. From 2007 to 2012, Dr. Hsu worked in Foxconn, CA, USA. In 2013, he was an Inpaq USA site country manager. He served in a senior manager in Primax Taiwan from 2014 to 2019. He owned rich sensor and optical signal process and artificial algorithm experience in finger print and face recognition sensor IC system design. He has published over 60 technical papers and patterns. His current research interests include the applications of high sensitive active matrix sensing system for face ID and large and thinnest optical finger print on 5G mobile under OLED panel or in cell OLED and high speed Serdes re-timer and Ultra wide band IC design.