Date & Time: 

2022 / 10 / 14 (Fri) 14:20 - 16:20

Location: 

Delta Building R216, NTHU

Speaker: 

 Tai-Hua Lu, Obe Wu, and Aaron Du

Qualcomm Taiwan Design Center CPU Team

Qualcomm Taiwan Multi-Media R&D Team

Topic: 

Overview of CPU Architecture Design and Reconfigurable Instruction Cell Array, RICA

Abstract: 

This speech is to introduce the work content of CPU team in Taiwan, which is divided into two parts:  CPU architecture and Performance team and CPU Design Implementation team.  CPU architecture and team focuses on exploring CPU and system architecture to achieve competitive CPU performance.   And CPU design implementation team focuses on CPU subsystem realization. In the seminar, we will introduce how to analyze and realize.

The Reconfigurable Instruction Cell Array, RICA, with Machine Learning Accelerator and SoC implementation are our important function and task on the multi-media Taiwan R&D team. With the rapid growth of the technical requirement of computer vision and image processing, RICA provides a kind of programmable solution on C-language without the turn-around time of IC manufacturing. This speech will introduce some applications on RICA and the reasons why we should use RICA. As a digital design team in Taiwan, we also share some parts on implementation to realize this RICA-SoC.

Biography: 

• Eduacation
  • National Cheng-Kung University
    • PHD degree, Electrical Engineering. 2010
    • Major: CPU micro-architecture exploration and software-based self-testing
• Experience:
  • ITRI. Duty Manager. 2012-2014
    • GPU architecture and performance exploration
  • MediaTek Inc. Technical Manager. 2014-2019
    • System performance, power, and thermal exploration for premium tier mobile SoC
  • Sifive Inc. Engineer, Sr. Staff. 2019-2021
    • RISC-V CPU architecture and performance exploration
  • Qualcomm Inc. Manager. 2021~now
    • Snapdragon CPU architecture and performance exploration for premium/high tier mobile SoC

• Eduacation
  • National Chiao-Tung University
    • Bachelor degree, Department of Computer Science. 2006-2010
    • Master degree, Institute of Computer Science and Engineering. 2010-2012
• Experience:
  • Taiwan Semiconductor Manufacturing Company. Senior Engineer. 2012-2015
    • EDA Implementation and Signoff tool enablement for new process node
  • MediaTek Inc. Technical Manager. 2015-2020
    • Static timing analysis and integration for premium tier mobile SoC
  • Qualcomm Inc. Engineer, Staff. 2020~now
    • Snapdragon CPU design implementation for premium/high tier mobile SoC

• Eduacation
  • National Tsing-Hua University
    • Master degree, Computer Science, 2004-2006
    • Major: Network ASIC Design / Video Streaming
• Experience:
  • MediaTek (Merged Mstar) Inc., Principal Engineer. 2008-2014
    • Smart Mobile-Phone Chip Design and Low-Power Architecture
  • Spreadtrum Communication Inc., Deputy Technical Manager. 2014-2020
    • Mobile-Phone Chip Design and Low Power Architecture
  • Vicore-Logic inc., Technical Manager. 2020-2020
    • Robot Chip integration and architect
  • Qualcomm Inc. Engineer, Staff. 2020~now
    • Reconfigurable Instruction Cell Array and SoC implementation