Date & Time: 

   2025 / 05 / 23  (Fri) 14:20 - 16:20

 

Location: 

   Delta Building R216, NTHU

 

Speaker: 

   葉先覺 教授

   Department of Electrical Engineering, California State University, Long Beach -Two-Path Parallel Cancellation ZP

 

Topic: 

  OTFS Systems for Mitigating Residual Carrier Frequency Offset

 

Abstract: 

 Orthogonal time frequency space (OTFS) schemes have received significant attention recently, especially for high mobility scenarios. OTFS is a new 2-dimensional (2D) modulation and multiplexing technique proposed as an alternative to orthogonal frequency division multiplexing (OFDM) for next generation standard and beyond. In implementation, the Inverse Symplectic Fast Fourier Transform (ISFFT) performs as a pre-processing block while the Symplectic Fast Fourier Transform (SFFT) works as a post-processing block to OFDM systems. While OTFS is a robust orthogonal modulation scheme, the received delay-Doppler (DD) domain signal faces inter-carrier interference (ICI) and interference to other users as the exactness of decomposing the channel, though theoretically orthogonal, is still at best an approximation of reality in time varying environment. At high carrier frequencies as in the 6GHz band used for Wi-Fi 6E systems, the residual carrier frequency offset (CFO) of practical crystals induces a non-negligible ICI, leading to performance degradation. By integrating the ICI parallel cancellation (PC) scheme into the zero-padding (ZP) OTFS system, we present two novel two-path PC OTFS systems with two architectures to mitigate the CFO). Without estimating the residual CFO, both systems improve bit error rate (BER). Simulation shows several dB of BER improvement for two-path PC OTFS systems over the regular OTFS system when residual CFO exists.

 

Autobiography: 

HEN-GEUL YEH (葉先覺) received the B.S. degree in engineering science from National Chen Kung University, Taiwan, Republic of China in 1978, and the M.S. degree in mechanical engineering and the Ph.D. degree in electrical engineering from the University of California at Irvine, Irvine, in 1979 and 1982, respectively. Since 1983, he has been with the Electrical Engineering Department, California State University Long Beach (CSULB), USA, and the Department Chair, 2016 - 2022. He was selected as a NASA JPL Summer Faculty Fellow twice, in 1992 and 2003, respectively. His research interests include DSP/communication/control algorithms development and implementation using FPGA and digital signal processors with applications to communication systems, smart grids, optimization, controls, and electrical event detection. He is a Professional Engineer in Electrical and was a recipient of five NASA Technology Brief and New Technology Awards from the National Aeronautics and Space Administration (NASA), He has received eight U.S. patents in signal processing, communication, and controls. He is a senior member of the National Academy of Inventors and IEEE.